This application relates to a delay locked loop, and more particularly, to a delay locked loop having a precise phase resolution and a precise phase locking range.
Clock and data recovery (CDR) based on a delay locked loop, especially CDR using a phase interpolator does not use a voltage controlled oscillator (VCO) and thus has the following advantages. First, the CDR using a phase interpolator is robust to power supply voltage noise because no jitter accumulation takes place. Second, the CDR using a phase interpolator is easily designed and has low power consumption because the CDR does not require a VCO at each link in applications using a multi-link. Third, the CDR using a phase interpolator requires only a small area, is easy to design, and is robust to power, voltage, temperature (PVT) variation because the CDR uses a digital loop filter.
However, in the CDR using a phase interpolator, algorithmic jitter takes place and there is a limit to realizing a high phase resolution. Moreover, trade-off between phase resolution and phase locking time occurs. In other words, when the phase resolution increases, the phase locking time also increases. When the phase resolution decreases, the phase locking time also decreases. In addition, since the CDR using a phase interpolator is a first-order feedback system, trade-off between phase resolution and frequency locking range also takes place.